Automatic preparation, verification, and generation of all necessary reports and submission of the verified chip designs to a shuttle run (tape-in), thus relieving fab’s valuable engineering staff of manual verification of design project data.
We have been using POLYTEDA's PowerDRC and PowerLVS tools on a regular basis for several years, for physical verification of many designs and in several process technologies. We find the tools reliable and easy to use, and find that the LVS error output is sensible and well organized at a level of complexity appropriate to the challenge of solving tricky LVS problems.
I am very impressed with POLYTEDA's PowerDRC/LVS in terms of both its stand-alone capabilities and its workflow. We cannot be more impressed with the first-pass success it enabled for our radiation-hard, UWB chipset using a design team that had no previous SOS experience, and little direct silicon RFIC experience as well. The integration with AWR's Analog Office seamlessly meant that we had literally no training. In summary, we are using POLYTEDA for SiGe work now because of the great experience it afforded us in SOS.