PowerDRC/LVS is an efficient and innovative cloud-ready tool for physical verification of integrated circuits (ICs) covering principal DRC and LVS tasks both in single- and multi-CPU modes.
The tool has been certified for process nodes up to 40nm by UMC fab. It was many times tested and evaluated against main competitive tool showing steady performance benefit, which grows with increasing of layout design size and complexity.
Lots of memory chips, microcontrollers, analog blocks and other IP were verified and proven in silicon with PowerDRC/LVS, thus the tool satisfies needs in PV of all European fabs and most fabs outside Europe.
It runs as сross-platform software, including industrial Linux 64 bit as primary OS, and it has been successfully tested to run in a cloud environment including Amazon AWS.
PowerDRC/LVS enables rapid verification of new designs to ensure accuracy, prior to mask creation and manufacturing.
The tool provides the following capabilities:
- DRC – design rules checking in layout
- LVS – layout vs. schematic verification
- NVN – schematic netlists comparison
- Checking of antenna rules, pads, latches
- Layer-by-layer XOR of full design
- Quick diffing of layout versions
- Graphical debugging, LVS cross-probing
- Fill layers generation
- Parasitic extraction
The listed capabilities cover the whole range of developer needs and meet modern industrial standards in layout design preparation for fabrication.