The Physical Verification Market

The worldwide market for PV tools (DRC/LVS and related tasks) is approaching $500M per year in license sales. The big 3 EDA vendors all have PV offerings:  Mentor with its Calibre nmDRC is the market leader; Cadence offers Assura/PVS; and Synopsys’ solution is named IC Validator. All three of these solutions are targeted to perform PV on very large designs including those at leading edge process geometries below 10nm. Consequently, these tools are high-value, but also quite expensive. While the PV technology is driven by the needs of the leading edge (process geometries < 10nm and die sizes > 700mm2) the broader market (designs in processes > 28nm) is quite willing to adopt more cost effective solutions if they can provide both accuracy and performance.

 Challenges for the Established PV Solutions

  • Non-linear dependencies in run times
  • Unpredictable behavior
  • Slow performance when running in flat mode on a single CPU
  • Performance and accuracy problems when the design contains non-Manhattan structures (any angles)
  • Limitations in multi-CPU scalability (typically 24 – 32 CPUs maximum)


Compelling Business Opportunity for PowerDRC/LVS

The broader market for integrated circuit design is found in process geometries that are larger than 28nm. Approximately 65% of the design activity occurs on processes that range from 40nm to as large as 3 microns (like process for MEMS devices). With the growing market for IoT, automotive, consumer and other markets the providers of these “older” processes are going through a revitalization and modernizing their processes and fabs. The technologies and equipment are being upgraded to support “add-ons” like MEMS, rad-hard devices, power management, image sensors, automotive and other sensors. These “add-ons” require new PDKs to be created with DRC/LVS run sets containing additional sections of thousands of complex rules that need to be checked on top of the standard process base.

This process expansion in the broader market creates a compelling business opportunity for PowerDRC/LVS.

PowerDRC/LVS Benefits

  • Predictable, linear runtimes due to One-Shot technology. PowerDRC/LVS establishes a small (adjustable) window that reads in multiple layers simultaneously and checks them. It then moves the window across the chip until the verification is complete. Since the processing time per window is known it makes the runtimes both predictable and linear. Optionally, PowerDRC/LVS can be used in hierarchical mode and perform cell array processing on-demand, but its architecture is natively flat. (Competing solutions are hierarchical leading to unpredictable runtimes).
  • PowerDRC/LVS is faster on logic and analog mixed-signal designs than the competition. Average run-times are competitive with the market leader (Calibre) and slower on very hierarchical designs such as memories and cell arrays. As more random structures are encountered in a design, PowerDRC/LVS becomes much more predictable in terms of runtime while the competition slows down or even goes flat.
  • PowerDRC/LVS offers very predictable performance of ~5 million transistors per hour per CPU at any process node above 28nm. It is scalable up to 128 CPUs.
  • PowerDRC/LVS’s powerful PWRL language allows rule decks to be created faster and yields decks that have 25-30% fewer lines.
  • PowerRDE provides a GUI cockpit for PV workflow and provides text and visual viewing of results.
  • PVCLOUD (the cloud-based implementation of PowerDRC/LVS) offers a unique pay-as-you approach to running the tool without needing to invest in expensive hardware, maintenance and support.


Foundry Support


Foundry Process Geometry Status
Silanna 500-250nm Certified 2011
UMC 180nm,65nm,40nm Certified 2012
IHP 250-130nm Certified 2017
TowerJazz 180nm Certified 2018
X-FAB 180nm Certified 2018
X-FAB 350nm In process
TSI 180nm In process
SCL 180nm In process

Breadth of Applications

  • CMOS/BiCMOS processes
  • Supports custom LCD/CDD
  • Rad hard processes
  • Silicon photonic processes
    Design Flow Integrations
  • National Instruments-AWR – Integrated with Analog Office/Microwave Office
  • Cadence – Virtuoso IC61+
  • Keysight – ADS 2016-2017
  • KLayout

Pricing and Other Specifications

  • Scalable for parallelization across up to 128 CPUs (proven)
  • Supported Operating Systems – Linux CentOS/RH 6-7; Windows 32/64 bit
  • Pricing: 1-year license starts at $10,000; Educational (limited functionality) version is licensed free of charge
  • Current version: PowerDRC/LVS GA version 2.4 release in July 2018


For More Information