Physical verification (PV) of an integrated circuit design is a critical step that must be completed prior to handing off a design to the foundry for manufacturing. It is a task that demands both performance and accuracy. Performance is required  to meet schedule requirements in a competitive marketplace where time-to-market is a key driver.

Accuracy is important to avoid re-spins, yield loss, or even outright failures in the finished chip. Chip designers are naturally concerned about trading off performance for accuracy or vice versa – both are important and cannot be sacrificed. A balance needs to be achieved between over- and under-checking the design.

Demonstrating the importance of physical verification tools, annual licensing revenue is approaching $500M per year. These tools are typically licensed for hosting and use within a customer’s computing and design environment. However, cloud-based physical verification is beginning to be adopted as a more cost effective solution for many segments of the market. Cloud-based physical verification is not only more cost effective but offers advantages in performance and accuracy that competing tools cannot deliver even at their higher price points.


Limitations in existing physical verification tools

The major physical verification tools that are available in the market today utilize hierarchical approaches for processing designs. The challenges for this approach are that runtimes are difficult to predict, particularly if accuracy demands running the tools in flat mode. In addition, these tools are limited in the degree of parallel processing that can be exploited to gain extra performance – 24 to 32 CPUs is typically the maximum achievable.

Some hierarchical PV tools place stringent requirements on how the layout is assembled. If the layout does not conform to these restrictions the tool will be forced into flat mode that can easily cause an order of magnitude slowdown in processing time. Accuracy is also a potential issue for hierarchical approaches when considering the boundaries at the hierarchical blocks and proximity effects which can lead to DRC violations that are missed.

The layout style can also lead to loss of accuracy. Most existing PV tools only support Manhattan geometries. A design with non-Manhattan elements may yield inaccurate results since the PV tool must break down the non-Manhattan elements into an approximation consisting of orthogonal segments.

Delivering performance and accuracy in cloud-based physical verification

POLYTED’s PVCLOUD solution leverages the availability of secure, readily available cloud computing and innovative technology to provide a high performance, high accuracy scalable solution for integrated circuit physical verification.  PVCLOUD delivers this via a secure, cost-effective cloud platform.

PVСLOUD’s innovative One-Shot DRC processing engine delivers on both performance and accuracy. It uses a window scanning approach that combines multiple rules and layer checks into a small and efficient memory footprint. Strip processing supports parallel processing scalability on up to 128 CPUs delivering throughput of up to 5 million devices per hour per CPU. This scalability and the on-demand nature of cloud computing allows design teams to make intelligent tradeoffs in processing performance, schedule and budget.

The One-Shot DRC processing engine has a near linear dependency between run time and input data size. The speed of DRC processing is directly proportional to the number of objects being processed and is constant for a given style of layout and process node. Unlike hierarchical approaches, designers can accurately predict in advance how long a given processing run in PVCloud will take.

PVCloud fully supports all-angled designs delivering higher accuracy for designs with non-Manhattan geometries. In certification tests at numerous foundries, it has been shown to find violations that other competitive solutions have failed to detect including errors in basic spacing, DFM rules and device extraction rules.

The sweet spots for PVCloud physical verification

PVClOUD has been optimized to deliver performance and accuracy over a wide range of applications and process geometries for integrated circuit designs with the cost-efficiencies of cloud-computing. PVClOUD is ideal for:

  • Silicon-based designs targeting digital, analog mixed-signal, MEMS, memory, photonics, rad hard, power management and RF
  • Process geometries from 40nm to 250nm
  • Fabless IC houses, IP design groups, and foundries

Key performance and accuracy benefits of PVClOUD

  • One-Shot technology supports scalable multi-CPU parallelism up to 128 CPUs
    • Scale up and down depending on performance needs and schedule
    • Natively flat design delivers the highest physical verification accuracy
  • Highly predictable run-times based on design size
    • Much more efficient use of resources – match performance needs to schedule through use of scalable multi-CPU processing
  • Supports any-angled design geometries
    • Delivers sign-off accuracy even for non-Manhattan geometries
  • Sign-off certified at multiple foundries for 40, 65, 130, 180 and 250 nm processes
    • Reduce project risk and costs
    • Accuracy: PVClOUD has been documented to find errors that other more expensive physical verification products have missed
  • Cloud-based solution allows control and tradeoffs for budget, performance, and schedule
    • PVClOUD works with the most widely used EDA tools and flows


About the author:

Alexander Grudanov is CEO of POLYTEDA CLOUD –

EENews Europe